System-Level Partitioning Using Mission-Level Design Tool for Electronic Valve Application 2003-01-0865

In defining innovative and cost-effective chip sets for future automotive applications, system architects need high-level tools that allow them to rapidly determine the best silicon partitioning for a given application in terms of system performance as well as cost. The tool needs to be flexible, modular, and swift such that the system designer can perform abstract simulation iterations quickly for various functional partitioning scenarios, without requiring excessive computer resources. The tool must also be portable and adaptable to provide a simulation environment suitable to systems- or car-manufacturers for in-depth applications simulation and architecture assessment.

The semiconductor component definition process using such a “mission-level” design tool for the automotive application electronic valve will be demonstrated. Methods for the analysis of electronic valve control system architectures using mission-level simulation will be developed. Simulation results and corresponding analysis of electromagnetic valve control performance within two primary types of system architectures, centralized and mechatronic, will be provided. Control algorithms using various sampling frequencies and accuracies for position and current data acquisition are included within simulation. Analysis will determine processing power needed to effectively follow and manage current dynamic and valve position. Timing diagrams of communication will characterize bus traffic in order to evaluate speed of communication busses between power devices and valve microcontroller, as well as between the VCU and ECU. The type of instructions to be processed by the valve control algorithm to deliver the appropriate output to the electromagnetic valve will be determined so that an appropriate microprocessor can be selected. A semiconductor architecture recommendation based upon simulation results and analysis, in addition to cost considerations, will identify a best-fit silicon strategy for the end application.