Advanced HW/SW Analysis for Multi-core MCU Systems with AUTOSAR OS Awareness

Paper #:
  • 2011-01-0446

Published:
  • 2011-04-12
Citation:
Reyes, V. and Schirrmeister, F., "Advanced HW/SW Analysis for Multi-core MCU Systems with AUTOSAR OS Awareness," SAE Technical Paper 2011-01-0446, 2011, https://doi.org/10.4271/2011-01-0446.
Pages:
11
Abstract:
Recent analysis shows that 90 percent of future innovation in Automotive will be based on electronics, for which a significant amount will be defined in embedded software [11]. The challenge for suppliers and vehicle manufacturers is to develop advanced software applications that offer optimized performance, while providing flexibility and reliability. To deal with the complexity cause by this shift to software defined functionality, the industry is adopting standards like AUTOSAR to provide a predefined interface between the MCU hardware and the software applications. In addition, to support the enhanced capabilities of those applications the industry is moving to more powerful multi-core MCU architectures, offering real-time and fail-safe capabilities. Moving forward, significant challenges will lie in testing the functionality and performance of such software applications running on top of the next generation multi-core architectures. As a result the debug and analysis of hardware/software interactions becomes a critical part of automotive design flows.This paper illustrates how complex interactions between software and hardware can be analyzed in a multi-core MCU system by using SystemC/TLM-2.0 standard based virtual prototyping technology. The analysis methods presented are able to visualize and correlate AUTOSAR tasks running on the different cores with software aspects, such as function and instruction traces, as well as hardware aspects, such as CPU load, bus throughput and memory access latency. The methodology has been proven with a virtual prototype of the Freescale MPC56xx MCU containing two e200 PPC cores. Furthermore, this work shows how these techniques scale to distributed networks of ECUs containing a multi-core MCUs.
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