Design verification technology promises comprehensive analysis of design models against the specified properties, thereby overcoming the limitations of traditional simulation-based and testing-based approaches. It helps in detecting design bugs early, thereby reducing the software development cycle time and cost. In this paper, we present our experiences with three state-of-the-art design verification tools - Reactis Validator, Simulink Design Verifier and Embedded Validator - for Simulink/Stateflow models. We also identify some challenges in employing them in an industrial production environment. We also suggest some automation steps to ease the design verification effort.