Applying Design Verification Tools in Automotive Software V&V

Paper #:
  • 2011-01-0745

Published:
  • 2011-04-12
Citation:
Chakrapani Rao, A., Rajeev, A., and Yeolekar, A., "Applying Design Verification Tools in Automotive Software V&V," SAE Technical Paper 2011-01-0745, 2011, https://doi.org/10.4271/2011-01-0745.
Pages:
7
Abstract:
Design verification technology promises comprehensive analysis of design models against the specified properties, thereby overcoming the limitations of traditional simulation-based and testing-based approaches. It helps in detecting design bugs early, thereby reducing the software development cycle time and cost. In this paper, we present our experiences with three state-of-the-art design verification tools - Reactis Validator, Simulink Design Verifier and Embedded Validator - for Simulink/Stateflow models. We also identify some challenges in employing them in an industrial production environment. We also suggest some automation steps to ease the design verification effort.
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