This paper approaches failure analysis in electronics under design for reliability (DfR) point of view. Some real cases illustrate how stress/strength interference (SSI) plays an important role to understand the component failure under the perspective of strength variation within a lot, from lot to lot and from manufacturer to manufacturer and likewise, the stress applied may vary with temperature, vibration etc. Also, the paper stresses the necessity to go beyond classical reliability practice, generally associated with minimizing catastrophic failures. For it, the real cases lessons learned are discussed looking for opportunities for future failure mode avoidance practices such as: a) derating for electronic components aiming to reduce the probability of the stress to exceed the strength of the part, b) worst-case circuit analysis (WCCA) i.e. under extreme environment or operating conditions and finally, c) the distinction between Design for Six Sigma (DFSS) and Design for Reliability (DfR).