Meta Model Driven Configurable Architecture Development and Validation

Paper #:
  • 2012-01-0006

Published:
  • 2012-04-16
DOI:
  • 10.4271/2012-01-0006
Citation:
Malliah, B., "Meta Model Driven Configurable Architecture Development and Validation," SAE Technical Paper 2012-01-0006, 2012, doi:10.4271/2012-01-0006.
Author(s):
Affiliated:
Pages:
10
Abstract:
Today many applications in the vehicle are demanding more processing power. Any change in architecture to accommodate continuous change in requirements is becoming more and more tedious. Therefore, the concept of fixed or hardcoded architecture approach will be finding limited applications in the future. Most of the system developers are moving towards a model driven approach to create the architecture from concept. Processor architecture models created must be configurable and accurately execute the newly configured instructions set. The architecture created could meet the processing demand of vehicle applications like powertrain, Infotainment, for example, in terms of, processing power, connectivity and standard interfaces. These architectural models could serve as good innovative platform for performance analysis, system characterization and failure mode analysis. It should be possible to execute the intended automotive applications on this platform and validate the system requirements at a very early stage of the development cycle. This requires a versatile platform that is itself independent of a particular architectural model. In this paper we describe how Sankhya's Meta model driven architecture development platform (SANKHYA Teraptor) fulfils such requirements and enables configurable models of processor architecture to be created, that can be used to simulate and execute the system applications.In this paper we describe the power of the SMDL and SSDL modelling languages and how quickly these enable the developer to build even a complex processor or system model. We also describe how the models developed meet the functional requirements as well as offer cycle accurate behaviour. This means different instruction sets can be configured and number of clock cycles to be executed can be programmed.In any complex processor development, simulation and verification of all the functions is a major challenge. In this paper we will describe how Teraptor will automatically generate test vectors and verify the design and how changes to configuration of the processor instruction set can be propagated to automated verification.In this paper, we will briefly describe how Teraptor can be used to synthesize the simulated and verified architecture to hardware prototype. This hardware implementation has the qualified specifications generated from performance validated model. One can get the major advantage of increased first time success in the implementation.
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