Serial WireRing - High-Speed Interchip Interface

Paper #:
  • 2012-01-0198

Published:
  • 2012-04-16
Citation:
Huck, T., Rohatschek, A., Thoss, D., and Todorov, S., "Serial WireRing - High-Speed Interchip Interface," SAE Technical Paper 2012-01-0198, 2012, https://doi.org/10.4271/2012-01-0198.
Pages:
7
Abstract:
A new high-performance interchip interface, called Serial WireRing, is introduced. It combines technically mature and established methods, whereby Serial WireRing provides a simple, robust and very inexpensive solution to replace the Serial Peripheral Interface (SPI). Serial WireRing uses a daisy chain ring topology, realized by unidirectional point-to-point connections from device to device. Serial WireRing is realized by a simple “wire ring” with CMOS, LVDS, optical or any other suitable signaling, even mixed. Therefore it has a very low pin count. In order to minimize the latency each slave transmits the data that it receives with 1 bit delay only. In order to avoid clock/data skew, the serial data and clock are merged into one bitstream. A corresponding clock is extracted at each receiver by a clock and data recovery circuit, driven by a simple internal oscillator. In this way additional clock networks can be omitted, since the introduced interchip interface supports inherently the clock distribution function. All nodes may operate their local data processing units with the recovered clock. The whole ring is operating synchronously, due to a single clock domain. Thus the system complexity can be significantly reduced. Further, the Serial WireRing protocol includes CRC information to detect transmission errors and initiate an automatic retransmission of disturbed frames, offering an easy integration into high safety-critical systems.
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