Improving the ESD Performance and Its Effects in CMOS - SOI/BULK Technologies and Automotive Electronic Components

Paper #:
  • 2014-36-0304

Published:
  • 2014-09-30
DOI:
  • 10.4271/2014-36-0304
Citation:
de Souza Fino, L. and de Souza, R., "Improving the ESD Performance and Its Effects in CMOS - SOI/BULK Technologies and Automotive Electronic Components," SAE Technical Paper 2014-36-0304, 2014, doi:10.4271/2014-36-0304.
Pages:
9
Abstract:
The reliability of the microelectronic devices and circuits is a major factor that determines both their manufacturability and application lifetime. One of the most pervasive problems on the integrated circuit (IC) industry is the electrostatic discharging (ESD) failure. ESD damage has become more prevalent in newer technologies due to the higher susceptibility of smaller circuit components. In addition, the changes on the IC technology have also changed the ESD protection techniques, requiring a continuous improvements and studies.ESD causes about 40 % of IC failures and represents, annually, a loss of billions of dollars due to repair, rework, shipping, labor and overhead costs associated with the damage, which highlights the importance of fundamental understanding of ESD aspects and design of efficient ESD protection. Considering these aspects, this paper will analyze the ESD effects in a single transistor and in a complex circuit (electronic modules), considering also the next generation transistors (SOI MOSFET) that need different solutions than those used in Bulk technology due different physical construction.The introduction of each new generation of silicon technology results in new challenges in terms of ESD capability, protection circuit design and the physical mechanisms, which can affect the transistors, electronic circuits, manufacturer process and the final product, such as a vehicle. On this way, this work also investigates the ESD robustness, covering the ESD controls, ESD failures and device physics, ESD testing, ESD protection and design methods and a technology robustness comparison.
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