Understanding how to Mitigate Failures Induced by Atmospheric Radiation with New Transistors Layouts for Processors

Paper #:
  • 2014-36-0306

Published:
  • 2014-09-30
DOI:
  • 10.4271/2014-36-0306
Citation:
de Souza, R. and de Souza Fino, L., "Understanding how to Mitigate Failures Induced by Atmospheric Radiation with New Transistors Layouts for Processors," SAE Technical Paper 2014-36-0306, 2014, https://doi.org/10.4271/2014-36-0306.
Pages:
7
Abstract:
This paper describes how new transistors layouts can mitigate failures Induced by atmospheric radiation, focusing on the total ionizing dose (TID) effects. By conducting an experimental comparative study of the TID effects between the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) manufactured with new layouts proposals and the standard layout (Conventional), for devices exposed to 10 keV X-ray irradiation using a Shimadzu XRD-7000 equipment, this paper suggests a new approach of layouts to have a better performance in radiation environment with low cost impact, lower power consumption, more speed and they could keep robustness and reliability.
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