The EU emergency call (eCall) system is used as a vehicle emergency telematic system to reduce the fatalities and save more lives in vehicular incidents. We have designed and implemented the CRC module for the in-vehicle system (IVS) of the EU eCall on an FPGA device. As the CRC is a crucial part of the system to detect bit errors during the transmission, this paper presents the hardware design procedures of the CRC module. The system reads the 1120 serial input bits of the Minimum Set of Data (MSD), calculates the 28-bits of the CRC parity bits, and generates the MSD appended with CRC as the output signal that is consisting of 1148 serial bits. The system is designed in Verilog HDL, compiled, synthesized, and simulated for different MSDs. The results are shown and analyzed for varied applied MSDs. The flowchart of the implemented algorithm is illustrated and discussed. The system is tested and verified for different frequencies to see the range of the applicable frequencies of the design. We noted that the higher frequency we use for the clock source, the more distortion we get in the generated signal. The generated signals for the clock frequencies 50 kHz, 5 MHz, and 10 MHz are discussed. The simulated MSDs and generated signals on the FPGA are compared for multi cases to analyze the performance of the module. We also used a developed CRC module for IVS in C code to verify the performance of the module.