Utilizing Behavioral Models in Experimental Hardware-in-the-Loop

Paper #:
  • 2016-01-2042

  • 2016-09-20
  • 10.4271/2016-01-2042
Miller, C. and Boyd, M., "Utilizing Behavioral Models in Experimental Hardware-in-the-Loop," SAE Int. J. Aerosp. 9(1):128-133, 2016, doi:10.4271/2016-01-2042.
This paper introduces a method for conducting experimental hardware-in-the-loop (xHIL), in which behavioral-level models are coupled with an advanced power emulator (APE) to emulate an electrical load on a power generation system. The emulator is commanded by behavioral-level models running on an advanced real-time simulator that has the capability to leverage Central Processing Units (CPUs) and field programmable gate arrays (FPGA) to meet strict real-time execution requirements. The paper will be broken down into four topics: 1) the development of a solution to target behavioral-level models to an advanced, real-time simulation device, 2) the development of a high-bandwidth, high-power emulation capability, 3) the integration of the real-time simulation device and the APE, and 4) the application of the emulation system (simulator and emulator) in an xHIL experiment. The first topic will be addressed by targeting a behavioral-level model of a brushless dc motor drive with a pulse-width modulated inverter to a real-time simulator. The results of the real-time model will be compared to that of its non-real-time counterpart. For the second topic, hardware descriptions and data will be presented showing the APE's ability to track high-frequency command profiles. The third topic will cover the communication requirements and methods used for integrating the real-time simulator with the APE. Finally, for the last topic, the APE and real-time simulator will be integrated to emulate the brushless motor's dc-link current drawn by the inverter in a hardware experiment. In using the APE and the real-time simulator, it will be shown that it is possible to run detailed electrical models in real-time and emulate detailed electrical characteristics in hardware without requiring the actual hardware component. In following this process, it is possible to reduce risk and accelerate hardware and software development.
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