Current generation automobiles are controlled by electronic modules for performing various functions. These electronic modules have numerous semiconductor devices mounted on printed circuit board. Solders are generally used as thermal interface material between surface mount devices and printed circuit boards (PCB) for efficient heat transfer. In the manufacturing stage, voids are formed in solders during reflow process due to outgassing phenomenon. The presence of these voids in solder for power packages with exposed pads impedes heat flow and can increase the device temperature. Hence it is imperative to understand the effect of solder voids on thermal characteristics of semiconductor devices. But the solder void pattern will vary drastically during mass manufacturing. Replicating the exact solder void pattern and doing detail simulation to predict the device temperature for each of the manufactured module is not practical. Hence, different numerical models are studied for the solder by using single and distributed void patterns matching the percentage void fraction. The above study is carried out for a range of percentage void fraction which is generally found from the solder X-ray images. These studies are performed on a MOSFET device that is very commonly used in automotive electronic modules. The numerical model used for the study consists of the MOSFET, solder and PCB. For a few devices, detail model of solder voids matching the pattern extracted from the corresponding X-ray images are created and simulated results are compared with numerically created single and distributed void pattern models. The comparison helped in selecting the best possible numerical void pattern model. Subsequently simulation is carried out using the best numerical void pattern for a range of power dissipation for the MOSFET. This aided in establishing the relationship between the device temperature rise and the percentage void fraction for a given power dissipation. The outcome of this study assisted in deciding the acceptability of the percentage solder void fraction for the MOSFET under consideration.