Solder Void Modeling and Its Influence on Thermal Characteristics of MOSFETs in Automotive Electronics Module

Paper #:
  • 2017-01-0011

Published:
  • 2017-03-28
Citation:
Sridharan, K. and Viswanathan, S., "Solder Void Modeling and Its Influence on Thermal Characteristics of MOSFETs in Automotive Electronics Module," SAE Int. J. Passeng. Cars – Electron. Electr. Syst. 10(2):283-289, 2017, https://doi.org/10.4271/2017-01-0011.
Pages:
7
Abstract:
Current generation automobiles are controlled by electronic modules for performing various functions. These electronic modules have numerous semiconductor devices mounted on printed circuit boards. Solders are generally used as thermal interface material between surface mount devices and printed circuit boards (PCB) for efficient heat transfer. In the manufacturing stage, voids are formed in solders during reflow process due to outgassing phenomenon. The presence of these voids in solder for power packages with exposed pads impedes heat flow and can increase the device temperature. Therefore it is imperative to understand the effect of solder voids on thermal characteristics of semiconductor devices. But the solder void pattern will vary drastically during mass manufacturing. Replicating the exact solder void pattern and doing detail simulation to predict the device temperature for each manufactured module is not practical. Hence different numerical models are studied for the solder, by using single and distributed void patterns matching the percentage void fraction. The numerical studies indicated that distributed void pattern captures the void behavior well compared to single void model. For the MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) device under study, it is observed that the void percentage up to 20% has negligible impact on device temperature for its maximum rated power. The temperature rise because of increase in void percentage (from 20% to 50%) for different power ratings of MOSFET is discussed in the paper. A risk rating chart is also provided as guideline for solder void rejection.
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