Shielded Gate Trench Technology for achieving the Best Performing Automotive MOSFETs in Medium Voltage Applications

Paper #:
  • 2017-01-0012

  • 2017-03-28
With an increasing demand for lower RDS(ON) FET in automotive applications, the use of shielded gate trench MOSFET architecture is gaining traction in medium voltage area for its ability to achieve lower RDS(ON) X AREA, and consequently, smaller chip size and lower cost. Additionally, shielded gate trench architecture features smaller gate-to-drain overlap, leading to lower G-D charge (QGD) and increased DV/DT immunity. Optimization of various elements of the shielded gate structure plays a critical role in achieving low specific RDS(ON), low gate charge (QG), low output capacitance (QOSS), and finally the best-in-class figure-of-merits (FOMs) - RDS(ON) X QG, RDS(ON) X QOSS. The optimization work includes TCAD simulation, process/device design of experiments of EPI thickness/doping profile in the drift region, trench gate and shield-plate structure optimization - trench depth, trench gate and shield-plate oxide thicknesses, and Si-mesa between the shield-plate trenches. Monte Carlo TCAD simulation using Synopsis tool is usually performed per automotive customer’s request to predict the expected electrical parametric distributions in production (min/max values for capacitances, QG, Trr, Qrr values, which are not usually present in the datasheet), in response to numerous process variations. The RDS(ON) reduction is achieved by lowering all resistance components along the drain to source current path, such as, substrate resistance is lowered by using thinner and heavier-doped red-phosphorus substrate material; EPI drift region resistance is lowered by using thinner and heavier-doped EPI material utilizing the shielding effect from the shield-gate structure to maintain the BVDSS; channel resistance is lowered by using the tighter cell pitch dimension utilizing finer CD process tool capability, and shallower body junction. The final paper will present the improvement in the device electrical parameters, parametric FOMs, and application circuit performance, including converter efficiency, avalanche and thermal capability of the shielded gate architecture.
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