At 2012, along with the demand of more and more data communication within ECUs, Bosch has proposed a new version of CAN named as CAN FD which can support data frame up to 64 bytes compared with 8 bytes of CAN. Because CAN data frame is limited at maximum 8 bytes, it is impossible to encrypt and secure CAN data, so it is transmitted through CAN bus in a raw format which makes CAN data is vulnerable to attack. With the of CAN FD over CAN in supporting bigger data frame up to 64 bytes, we propose a hardware design - CAN crypto FPGA chips to secure data transmitted through CAN FD bus by using AES-128 algorithm and SHA-1 with a symmetric key . AES-128 will provide confidential of CAN message and SHA-1 with symmetric key (called as Key SHA-1) can be considered as HMAC which will provide integrity and authentication of CAN message. Moreover, hardware shall provide more security for cipher key, symmetric key, or asymmetric keys over software. The design has been modeled and verified by using Verilog HDL – a hardware description language, and implemented successfully into Xilinx FPGA chip by using simulation tool ISE (Xilinx). Verifications are done by applying direct test bench with National Institute of Standards and Technology (NIST) test vectors for AES-128 and SHA-1 algorithms. The performance of the designs implemented in Xilinx FPGA chips are 187 MHz maximum clock frequency – 203 Mbps throughput for encryption chip, and 182 MHz maximum clock frequency – 198 Mbps throughput for decryption chip. The performance of CAN crypto encryption and decryption chips show that they are applicable to be embedded into ECUs for securing data transmitted through CAN FD bus.