System Verilog / UVM for Complex FPGA Verification in Aerospace Applications

Paper #:
  • 2017-01-2106

  • 2017-09-19
Avionics industry is tending towards more intelligent, more sophisticated and more electric aircrafts thereby increasing the complexity of in-flight hardware elements. Field Programmable Gate Array (FPGA) being one of the most critical and complex component in Airborne Electronic Hardware, its firmware design and development time is directly proportional to the complexity of the Airborne Electronic Hardware. As the complexity of the Firmware design increases, it becomes a humongous task to verify the Firmware. System Verilog based Universal Verification Methodology (UVM) is a key verification methodology which provides a complete verification environment, employing best features of System Verilog like Constraint Random Generation, Assertion Based Verification, Coverage Driven Verification and Re-usability. Built-in Classes, objects and tasks/procedures leads to reduced development time. This paper discusses on advantages System Verilog based UVM provides over other traditional FPGA verification languages used for Firmware verification in Aerospace. Since RTCA/DO-254/ED-80 are industry standards for Design Assurance Guidance for Airborne Electronic Hardware, this paper discusses the challenges and the opportunities System Verilog and UVM provides for getting the Airborne Electronic Hardware RTCA/DO-254/ED-80 certified. The paper also points out the advantages and benefits it provides to the avionics manufacturers. DO-254 compliant tools for simulation have been considered as key factors for trade off analysis of FPGA verification with System Verilog v/s Verilog and conventional VHDL methodology. This paper attempts to carry out analysis on impact, relation and applicability involved in various FPGA verification methodologies. Detailed study of various FPGA verification methodologies, considering verification environment development time, coverage analysis, challenges with respect to certification and reusability approach will be discussed. Study will be made on both Quantitative and Qualitative analysis of various verification methods and will be discussed in this paper. Outcome of the study with respect to the limitations and way forward for the new verification methods using UVM in aerospace will be presented in detail. Possible case studies will be presented in this paper.
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