IN May 1977, Control Data shipped the first AN/AYK-14(V) computer. This standard Navy airborne computer is a modular general-purpose 16-bit digital computer. It had a single processor instruction throughput of up to 480 KOPS based on the Gibson instruction mix. Included in the computer were three dual redundant MIL-STD-1553A I/O channels. Users quickly took advantage of the performance. However, with high serial bus activity of all three I/O channels, the instruction throughput was reduced to nearly zero. Help was on the way in the form of a second processor to control all three I/O channels. This I/O processor was introduced later in 1977 and was the beginning of “SMART” I/O for the AN/AYK-14(V).
The whole idea of “SMART” I/O developed when users and manufacturers alike saw the dramatic processing performance improvement with the addition of a second processor. In the late 1970's, the growth of “SMART” I/O was limited by technology. With the advent of VLSI technology and chip carrier packaging technology, the “SMART” I/O concept again gained momentum. A new level of performance in processor throughput and serial bus activity can now be realized.
Control Data has developed a preplanned product improvement (P3I) for the AN/AYK-14(V) family. The first P3I computer was shipped in July 1985. This computer includes a configuration with two 1-MIP processors and five smaller I/O processors. Each I/O processor controls a dual redundant MIL-STD-1553A/B channel.
