Use of One ST9 Timer for Handling a J1850 50 Kbit/Sec. Implementation

Paper #:
  • 910710

Published:
  • 1991-02-01
Citation:
Malusardi, P., "Use of One ST9 Timer for Handling a J1850 50 Kbit/Sec. Implementation," SAE Technical Paper 910710, 1991, https://doi.org/10.4271/910710.
Author(s):
Pages:
9
Abstract:
This paper describes a mixed hardware and software implementation for the SAE-J1850 protocol (1). This implementation is general and can be adapted to most J1850 based systems. Each node is entirely managed by one ST9 microprocessor. That means that the same micro controls the application and the bus.To interface with the bus the micro uses one ST9 16-bit timer and two register banks. As a result this system can be implemented using any ST9 microprocessor.Only a simple external circuitry is needed to drive and buffer the bus, as well as filtering the incoming signals. Bit decoding, CRC check/generation and consistency checks are done internally to the micro, thanks to the sophisticated hardware of the standard ST9 16-bit timer.The data link, network, transport, session and presentation layers are implemented by software. Therefore this implementation is perfectly suited for nodes with application layers of medium complexity, such as doors, lights, speed control, A/C control, instrumentation, distributed audio modules, etc.
Access
Now
SAE MOBILUS Subscriber? You may already have access.
Buy
Select
Price
List
Download
$27.00
Mail
$27.00
Members save up to 40% off list price.
Share
HTML for Linking to Page
Page URL

Related Items

Article
2017-03-13
Training / Education
2007-03-01
Technical Paper / Journal Article
2010-04-12
Training / Education
2010-03-15