Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit

Paper #:
  • 950035

Published:
  • 1995-02-01
Citation:
Sferrazza, P., Halter, R., and Stark, J., "Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit," SAE Technical Paper 950035, 1995, https://doi.org/10.4271/950035.
Pages:
21
Abstract:
As a cost effective solution to making microcontroller based systems “J1850[1] aware”, a peripheral device (the HIP7010) was developed to extend the capabilities of standard microcontrollers. From the perspective of the Host, the peripheral device handles J1850 messages as a series of bytes (similar in concept to a universal asynchronous receiver/transmitter [UART]).The architecture of the HIP7010 is discussed. The design of the J1850 interface, state machine, status/control blocks, cyclical redundancy check (CRC) hardware, host interface, and fail-safe features are detailed. Illustrations are provided of: Host/HIP7010 interfacing; message transmission and reception; error handling; and In-Frame Response (IFR) generation.
Access
Now
SAE MOBILUS Subscriber? You may already have access.
Buy
Select
Price
List
Download
$27.00
Mail
$27.00
Members save up to 40% off list price.
Share
HTML for Linking to Page
Page URL

Related Items

Training / Education
2010-03-15
Technical Paper / Journal Article
2010-10-25