An Architecture for Electronic Throttle Control Systems 2003-01-0098
This paper presents an architecture for monitoring and controlling an electronic throttle control system. The architecture contains two processors, the MAIN and the MCP. The MAIN is responsible for calculating the desired throttle position and the MCP for positioning the throttle using feedback control. The two processors measure all pedal and throttle sensors redundantly and continuously monitor the state-of-health of the other processor. Depending on the fault(s) detected, actuator default position, limited throttle authority, forced idle, Bowden cable mode or engine shutdown remedial action may be taken.
Citation: Costin, M., Schaller, R., Maiorana, M., Purcell, J. et al., "An Architecture for Electronic Throttle Control Systems," SAE Technical Paper 2003-01-0098, 2003, https://doi.org/10.4271/2003-01-0098. Download Citation
Author(s):
Mark Costin, Robert Schaller, Mario Maiorana, James Purcell, Robert Simon, Paul Bauerle, Jack Stockbridge
Affiliated:
GM Powertrain
Pages: 7
Event:
SAE 2003 World Congress & Exhibition
ISSN:
0148-7191
e-ISSN:
2688-3627
Also in:
Electronic Engine Control Technologies, 2nd Edition-PT-110, Software/Hardware & Systems Engineering-SP-1781, SAE 2003 Transactions Journal of Passenger Cars - Electronic and Electrical Systems-V112-7
Related Topics:
Throttles
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