BIST Based Method for SEE Testing of Vikram1601 Processor 2024-26-0433

A novel method for Single Event Effect (SEE) Radiation Testing using Built-In Self-Test (BIST) feature of indigenously developed Vikram1601 processor is discussed. The novelty is that the usage of BIST avoids need of exhaustive test vectors to ensure test coverage of all the internal registers and physical memory to store them. So processor is the only element vulnerable to radiation damage during testing. The test design was carried out at VSSC, Trivandrum and the testing was carried out at IUAC, Delhi. In the first part, a brief introduction, need and methods of radiation testing of electronics especially SEE of radiation on Silicon based devices, different radiation effects, radiation damage mechanisms and testing methods are described. A brief introduction to Vikram1601 processor, the instruction – TST, used as BIST and testing scheme implementation using TST for studying the SEE is explained. Radiation test facilities are explained with respect to the types of testing possible, capabilities, radiation particle species and maximum energies possible, size limitations of Silicon under test and System under test, duration of test for each species and energy etc. In the second part, the implementation of the testing scheme using an FPGA based system as checkout for online monitoring of the Vikram1601 Processor (mounted on a PCB along with necessary circuitry for operation) during irradiation is and lab level validation (without irradiation) of the checkout, harness design etc. are detailed. The actual SEE radiation testing conducted at IUAC with all the set-up requirements, procedure and results are detailed subsequently. Testing with Nickel beam (33 MeV LET) caused 5 SEUs (Single Event Upsets) while testing with Gold beam (64 MeV LET) caused 15 SEUs.