Synergized Mixed-Signal System-on-Chip (SoC) Design and Development using System-level Modeling and Simulation 2024-26-0463

In recent decades, research based innovative system-on-chip (SoC) design has been a very important issue, due to the emerging trends and application challenges. The SoCs encompass digital, analog and mixed-signal hardware and software components and even sensors and actuators. Modelling and simulation constitute a powerful method for designing and evaluating complex systems and processes for many analysts and project managers as they engage in state of-the-art research and development. Modelling and simulations not only help them with the algorithm or concept realization and design feasibility, but it also allows experimentation, optimization, interpretation of results and validation of model. As one more step, towards the strategic implementation of Complex SoC design and verification, we adopted “Synergized SoC design flow with Modelling and Simulation”, where the Modelling and Simulation process is in line with the SoC design and development process to address the design and verification needs and challenges, also to reap the maximum benefits of synergistic flow to build the complex, cutting edge technology based SoCs for emerging trends. The first section in this paper describes the process of leveraging system level modelling and simulation for algorithm design and development, for specification finalization with performance analysis and optimization for end-applications. The second section describes harnessing the model as a reference for hand written RTL validation and debug using HDL co-simulation infrastructure. The third section describes re-use of model for UVM (Universal verification Methodology) components generation and customization for SoC verification and FIL (FPGA-in-Loop) flow to accelerate FPGA design validation. The next section describes the automated flow for verification including test plan, test scenarios, test and coverage report generation using Simulink® Test Manager. The final section gives an overview of GUI creation for input generation and visualization of results and standalone EXE from the GUI developed for functional analysis.